Study of the I-V characteristic of JFET.

 AIM: To study the I-V characteristic of JFET.


 JFET, Breadboard, resistor (1KΩ, 1KΩ), connecting wires, Ammeters (0‐30mA), DC power supply (0‐10V) and a multimeter.



Construction & Characteristics of JFET

 The major part of JEET is the channel between embedded P types of material. The top of the n-channel is connected to an ohmic contact called ‘Drain’ (D) & lower end of Channel is called as ‘Source’ (S). The two p types of materials are connected together & to the ‘Gate’ terminal (G).

1. The gate is directly connected to the source to achieve VGS = 0V, this is similar to no bias condition. The instant the voltage VDD (=VDS) is applied, the electrons will be drawn to the drain terminal, causing ID & IS to flow (i.e. ID = IS). Under this condition, the flow of charge is limited solely by the resistance of the n channel between drain & source.

It is important to note that the depletion region wider at the top of both p-type of material. Since the upper terminal is more R .B. than the lower terminal (source - S).

As voltage VDS is increased from 0 to a few volts, the current will increase as determined by Ohm's law. If still VDS is increased & approaches a level referred to as VP, the depletion region will widen, causing a noticeable reduction in channel width. The reduced path of conduction causes the resistance to increase. The more the horizontal curve, the higher the resistance.

If VDS is increased to a level where it appears that the two depletion region would touch each other, the condition referred to as ‘pinch–off’ will result. The level of VDS that establish this condition is called as ‘pinch off voltage’ (VP). At VP, ID should be zero, but practically a small channel still exists & very high-density current still flows through the channel.

As VDS is increased beyond VP, the saturation current will flow through the channel (i.e. IDSS).
IDSS – Drain to source current with a short cut connection from the source to Gate.

2. VGS < 0V:-

If a –ve bias is applied between gate and source, the effect of the applied –ve bias VGS is to establish depletion region similar to those obtained with VGS = 0V but at the lower level of VDS.

As VGS will become more & more –ve biased, the depletion layer pinches off occurs at the less & less value of VDS. Eventually, when VGS = - VP, will be sufficient –ve to establish a saturation level, i.e. essentially 0 mA & for all practical purpose the device has been ‘turned OFF’.

The region to the right of the pinch-off locus is typically employed in linear amplifiers (Amplifier with minimum distortion at applied signal) is commonly referred to as the constant current, saturation or linear amplification region.



1. Connect the circuit as per the given diagram properly.
2. Keep VGS = 0V by varying VGG
3. Vary VDS in the step of 1V up to 10 volts and measure the drain current ID. Tabulate all the readings.
5. Repeat the above procedure for VGS as -0.5, -1V, -1.5V, -2V, -2.5V, -3V, -3.5V etc


1. Connect the circuit as per the given diagram properly.
2. Set the voltage VDS constant at 10 V.
3. Vary VGS by varying VGG in the step of 0.5 up to 3.5V and note down the value of drain current ID.
Tabulate all the readings.
7. Plot the output characteristics VDS vs ID and transfer characteristics VGS vs ID.


At VGS=0v,-0.4v,-0.6v respectively.

1. Drain saturation current IDSS: Maximum current flowing through JFET when the gate to source voltage is zero.

2. Transconductance gm: Ratio of small change in drain current (Δ ID) to the corresponding change in the gate to source voltage (ΔVGS) for a constant VDS.
gm = Δ ID / ΔVGS at constant VDS


I-V characteristics of JFET have been studied.